Process for fabricating copper interconnect for ULSI integrated circuits

ABSTRACT

A method for manufacturing integrated circuits; particularly, a method for fabricating a copper interconnect system and a copper interconnect system, having a layer of CrO, fabricated by the method.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to a method of manufacturing semiconductorintegrated circuit interconnect structures. The invention relates moreparticularly to a method for fabricating a copper interconnect systemand a copper interconnect system, having a layer of CrO, or chromiumoxide, fabricated by the method.

[0003] 2. Background of the Invention

[0004] Semiconductor integrated circuit devices typically comprisesilicon and multiple layers of vertically stacked metal interconnectlayers with dielectric materials disposed between the metal layers. Thefabrication of such devices typically involves the repeated depositionor growth, patterning, and etching of thin films of semiconductor,metal, and dielectric materials. Multiple metallization layers areemployed to accommodate higher densities as device dimensions shrink tosub-micron levels and dielectric materials are utilized to separate themetallization, or conductive, regions. Contact openings are formed inthe dielectric overlying a substrate region to provide conductivepathways to a source, drain and gate regions from a first metal layer.Via openings are formed in subsequent inter-level dielectric (ILD)layers separating various metal layers to provide conductive pathwaysbetween the metal layers.

[0005] A passivation layer is often deposited over a top metal layer asan insulation and protection layer to prevent mechanical and chemicaldamage during assembly and packaging. To deposit the passivation layer,the wafer surface may be backsputtered, if needed, and one or two layersof inorganic silicon oxide and/or silicon nitride and/or siliconoxynitride is deposited by chemical vapor deposition. The passivationlayer typically has 4000Å of silicon oxide and 3000Å of silicon nitride,or 10000Å of silicon oxide, where 4000Å is etched back, and 3000Å ofsilicon nitride. Other common passivation layers have a single coatingof 3000Å of silicon nitride. An organic spin-on dielectric, such aspolyimide, is also sometimes used on top of the inorganic dielectric toform the passivation layer.

[0006] One common metal used for forming metal lines, or wiring, on awafer is aluminum. Aluminum is relatively inexpensive, has a lowresistivity, and is relatively easy to etch. Aluminum has also been usedas a material for forming interconnections in vias to connect thedifferent metal layers. However, as the size of the via, or contactholes, is decreased to sub-micron levels, a step coverage problemoccurs, which has led to reliability problems when using aluminum toform the interconnection between different wiring layers. The poor stepcoverage in the sub-micron vias results in high current density andenhances electromigration, which is the transport of metal ions throughconductors resulting from passage of direct electrical current.

[0007] Metals, such as tungsten, have been used to improveinterconnection paths. Aluminum is used for the wiring, while tungstenplugs provide the interconnection between the different levels ofwiring. However, the tungsten processes are complicated and expensive.Tungsten has a high resistivity, and tungsten plugs are susceptible tothe presence of voids and form poor interface with the wiring layers,resulting in high contact resistance.

[0008] Copper is now being used for ULSI metallization because of itslower bulk electrical resistivity and its superior resistance toelectromigration and stress voiding, as compared to commonly usedaluminum and its alloys. Specifically, copper has a betterelectromigration property and lower resistivity than aluminum and betterelectrical properties than tungsten. Thus, copper is a desirable metalfor use in wiring and plugs.

[0009] A typical semiconductor with copper metallization includes acopper metallization film directly deposited onto a patterned insulatingfilm, such as SiO₂ film, which is deposited on a silicon substrate andover contact holes and trenches formed in an insulating film so as to bepositioned on diffused layers formed in the silicon substrate. Thecopper film is then polished back to leave only copper in the trenchesand contact holes in accordance with a wiring pattern and then annealedat a temperature of about 400° C. to grow grains of copper and improveelectromigration resistance.

[0010] One of the problems with copper is that it is difficult to etchafter deposition to form lines or via plugs. As a result, substantialtime and expense is needed to etch copper. Chemical mechanical polishinghas been used to polish away the unwanted copper material, but may beexpensive and timely. Alternatively, copper may be selectively depositedwithin the vias to form plugs, which eliminates the polishing step. Onetechnique to selectively deposit copper is electroless deposition, whichrequires activation of a surface to electrolessly deposit copper and isperformed after placement of a barrier layer for isolation from anadjacent dielectric layer. The copper plug must also be encapsulated inthe via.

[0011] Another major problem with copper is its fast diffusion in Si anddrift in SiO₂-based dielectrics, resulting in the deterioration ofdevices at low temperatures. A reaction and interdiffusion betweencopper in the metallization film and Si included in the substrate, orcopper in the metallization film and Si in the insulating film, mayoccur during annealing or other heat treating processes. This reactionor interdiffusion may occur because the copper metallization film isdirectly in contact with the Si substrate at the through holes in theinsulating film and causes an increase in contact resistance anddegradation of the copper metallization. Barrier failure is caused bydiffusion of copper along grain boundaries or through defects generatedat elevated temperatures in the barrier films, which are relativelyintact, or by the reaction between barrier films and Si formingmetal-rich suicides. Thus, it is necessary to prevent the reaction andinterdiffusion between Cu and Si.

[0012] A semiconductor device that addresses the problem of reaction andinterdiffusion is known. This device has a silicon substrate, aninsulating film in which a contact hole is formed, a metallic layerdeposited on the silicon substrate through the contact hole for formingan ohmic contact to the silicon substrate, a barrier layer deposited onthe metallic layer for preventing reaction and an interconnectionbetween copper and silicon, and a metallization film including copperdeposited on the barrier layer.

[0013] Another semiconductor device is known to prevent oxidation ofcopper at wire bonding in a pad electrode using a thin film havinganti-oxidation and anti-diffusion properties. This thin film is made ofmetallic material, such as Ti, W, Ta, or a compound of Al₂O₃, TiN,TiSi₂, and WSi₂. In general though, transition metals are not stablediffusion barriers between copper and silicon or between copper andwire-bond metal or solder-bump metal. Adding Si to refractory materials,Ta, Mo, and W, to form an amorphous refractory metal-Si diffusionbarrier improves barrier performance. A conductive metal-oxide diffusionbarrier can survive thermal anneals up to between 500-600° C.Copper-oxide tends to form at the metal-oxygen /copper interface athigher temperatures.

[0014] Another problem associated with copper interconnect isdegradation in bondability for bare die stored under normal conditions.The prior art addresses this problem by storing wafers under drynitrogen or using organic-protective coating on bond pads, but this canbe expensive.

[0015] Thus, it is desirable to have a method for fabricating copperinterconnect that has an improved electromigration resistance, hasbetter performance/reliability for wire bonds, enables conventionalpassivation layer processes to be used, and allows wafers to be storedfor extended periods of time before assembly.

SUMMARY OF THE INVENTION

[0016] The invention is a method of manufacturing an integrated circuitincluding the steps of: (1) providing a wafer having an inter-leveldielectric film and a barrier layer; (2) depositing a seed layer ofcopper on the barrier layer; (3) electroplating copper to a thicknesssufficient to fill in any valleys in the inter-level dielectric film andcover an entire top surface of the wafer; (4) chemical mechanicalpolishing the top surface to remove i) any excess portions of coppercaused by the electroplating and ii) selected portions of theinter-level dielectric film; (5) depositing a layer of CrO on thepolished top surface to cover remaining portions of the copper; (6)depositing a passivation layer on the layer of CrO and portions of theinter-level dielectric film; and (7) etching the passivation layer toform a via that exposes a selected portion of the layer of CrO.

[0017] Another aspect of this invention is an integrated circuitcomprising a wafer having a surface, a copper layer and an inter-leveldielectric film formed on selected portions of the surface, a seed layerand a barrier layer formed between the copper layer and the inter-leveldielectric film, a layer of CrO deposited substantially uniformly on topof the copper layer, a passivation layer covering any exposed portionsof the copper layer and the inter-level dielectric film, and a viaformed in the passivation layer exposing the layer CrO.

[0018] In yet another aspect of this invention is a method ofmanufacturing an integrated circuit including the steps of: (1)providing a wafer having bond pads comprised of a barrier layer, a seedlayer formed thereon, and copper formed on said seed layer; (2) forminga layer of CrO on the copper (3) forming a passivation layer on thelayer of CrO; and (4) etching the passivation layer to form a via thatexposes the layer of CrO.

[0019] In yet another aspect of this invention is an integrated circuitincluding a bond pad, having a barrier layer, a seed layer formed on thebarrier layer, a copper layer formed on the seed layer, and a layer ofCrO covering the copper layer, formed in an inter-level dielectric film;and a passivation layer formed on any exposed portion of the copperlayer, the inter-level dielectric film, and a selected portion of thelayer of CrO.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020]FIG. 1 is a cross-sectional view of a portion of a multi-levelmetallization integrated circuit manufactured in accordance with a firstaspect of the invention.

[0021]FIG. 2 is cross-sectional view of a portion of an integratedcircuit manufactured in accordance with a second aspect of theinvention.

[0022]FIG. 3 is cross-sectional view of a portion of a multi-levelmetallization integrated circuit manufactured in accordance with thesecond aspect of the invention.

DETAILED DESCRIPTION

[0023] The invention will be understood more fully from the detaileddescription given below, which however, should not be taken to limit theinvention to a specific embodiment, but is for explanation andunderstanding only.

[0024] A first method of the invention is a method of manufacturing anintegrated circuit including the steps of: (1) providing a wafer havingan inter-level dielectric film and a barrier layer; (2) depositing aseed layer of copper on the barrier layer; (3) electroplating copper toa thickness sufficient to fill in any valleys in the inter-leveldielectric film and cover an entire top surface of the wafer; (4)chemical mechanical polishing the top surface to remove i) any excessportions of copper caused by the electroplating and ii) selectedportions of the inter-level dielectric film; (5) depositing a layer ofCrO on the polished top surface to cover remaining portions of thecopper; (6) depositing a passivation layer on the layer of CrO andportions of the inter-level dielectric film; and (7) etching thepassivation layer to form a via that exposes a selected portion of thelayer of CrO.

[0025] Preferably, the inter-level dielectric is an inorganic compound,such as silicon oxide, silicon nitride, silicon oxynitride, or mixturesthereof, or an organic compound. Particularly preferred is aninter-level dielectric layer having SiO₂. The barrier layer ispreferably Ta, TaN, TiN, Ti, W, WN, TiSiN, TaSiN, or mixtures thereof

[0026] The barrier layer may be backsputtered before the seed layer isdeposited to improve adhesion of the seed layer. Sputtering is thepreferred method to deposit the seed layer of copper, but it may also bedeposited by chemical vapor deposition. After electroplating the copper,the chemical mechanical polishing removes any excess copper and theselected portions, such as the highest spots of the inter-leveldielectric film, so that what remains are vias and/or trenches that arefilled just to the top.

[0027] The layer of CrO may be deposited either by sputtering Cr in thepresence of O₂ or by evaporating Cr in the presence of O₂. If theseprocesses are utilized, then the CrO must be patterned using lithographyto remove the CrO on the inter-level dielectric film. Alternatively, thelayer of CrO may be deposited by autocatalytic plating. The resultingCrO layer covers the copper. In practice, an overhang head is likely tobe used to completely cover all of the copper edges.

[0028] The preferred thickness of CrO depends on the mechanicalproperties of the layer of CrO, which in turn depends upon theparticular process used to deposit the layer of CrO. The preferredthickness for common depositions is about 150-600Å and particularlypreferred is an optimum thickness of about 300Å. Chromium adheres wellto copper, thus preventing electrotransport of copper at the topsurface. In this invention, oxidation of the copper surface is preventedup to about 400° C. Copper oxide is detrimental because it greatlyincreases contact resistance and causes subsequent layers to have verypoor adhesion.

[0029] The passivation layer maybe silicon dioxide, silicon nitride,silicon oxynitride, doped versions of these materials, or mixturesthereof Typical dopants are fluorine and boron. The passivation layer ispreferably deposited by chemical vapor deposition, but may also bedeposited by a spin-on dielectric glass or polymer process or acombination of these processes. The passivation layer is etched to forma via that exposes a selected portion of the CrO layer to either enablewire bonding, or solder bumping, to the top level of metal or to enablethe next level of metal to contact the lower levels of metal. Theselected portion exposed is dependent upon the area necessary for wirebondings, solder bumping, or deposition of the next level of metal.

[0030] A portion of a multi-level interconnect structure manufactured inaccordance with the first method is shown in FIG. 1. The integratedcircuit includes a wafer 1 having a surface 2 and three levels ofmetallization 5, 10, and 15. The first level 5 includes an inter-leveldielectric layer 3 formed on the surface 2, a barrier layer 4 formed onthe dielectric layer 3, a seed layer 6 formed on the barrier layer 4,and copper 17 formed on the seed layer 6. The second level 10 has aninter-level dielectric 7 formed on the first level 5, a barrier layer 8formed on the dielectric layer 7, a seed layer 18 formed on the barrierlayer 8, and copper 9 formed on the seed layer 18. The third level 15has an inter-level dielectric layer 11 formed on the second level 10, abarrier layer 12 formed on the dielectric layer 11, a seed layer 19formed on the barrier layer 12, and copper 13 formed on the seed layer19. The third level also has a layer of CrO 14 formed uniformly inthickness on top of the copper 13. A via 20 is formed in the passivationlayer 16 to expose a portion of the layer of CrO 14. A passivation layer16 is formed on top of the third level 15 and covers portions of thedielectric layer 11 and may cover portions of the layer of CrO 14, seedlayer 19, barrier layer 12, and copper 13. The interconnect structuremay also have only one metal layer where the above-described third levelof metallization is directly located on the surface of the wafer.

[0031] A second method of the invention is a method of manufacturing anintegrated circuit including the steps of: (1) providing a wafer havingbond pads comprised of a barrier layer, a seed layer formed thereon, andcopper formed on the seed layer; (2) forming a layer of CrO on thecopper; (3) forming a passivation layer on the layer of CrO; and (4)etching the passivation layer to form a via that exposes a selectedportion of the layer of CrO. This method of the invention is used forbond pads on the top level, which in this case is copper. The bond padsare the features in the top-level metal used to connect a chip to theinterconnect. Chromium provides a good glue layer for under-bump metalstack on bond pads for wire bond. The bond pads may also be used forsolder bumps for flip chip packages.

[0032] A portion of an interconnect structure manufactured in accordancewith the second method is shown in FIG. 2. Inter-level dielectric layer21 has been etched to form a trench in the shape of a bond pad. The bondpad 30, within inter-layer dielectric 21, includes a barrier layer 22, aseed layer 28 formed on the barrier layer 22, and a copper layer 23formed on the seed layer 28. A layer of CrO 24 completely covers thecopper layer 23 and a passivation layer 25 is formed on an exposedportion of the inter-level dielectric layer 21. A small portion of thepassivation layer 25 usually covers a portion of the bond pad 30 toensure a complete seal around the edges of the bond pad. A via 51 isformed in the passivation layer 25 to expose a portion of the layer ofCrO 24. A wire bond is formed by a metal wire 27 and a ball-bondmaterial 26. During the bonding process, once a bond is formed betweenball-bond material 26 and the copper layer 23 and layer of CrO 24, themetal wire 27 is pulled away for making connection with a lead finger(not shown).

[0033] Another portion of an interconnect structure manufactured inaccordance with the second method, as shown in FIG. 3, is a multi-levelinterconnect structure. This bond pad 50 is in a trench of inter-leveldielectric layer 31, and includes a barrier layer 32 formed on a portionof the inter-level dielectric layer 31, a seed layer 29 formed onbarrier layer 32, and a copper layer 33 formed on the seed layer 29. Alayer of CrO 34 completely covers the copper layer 33 and a passivationlayer 35 is formed on the layer of CrO 34 and portions of theinter-level dielectric layer 31. A barrier layer 7 is formed on thepassivation layer 35, a metal layer 36 is formed on the barrier layer37, and an inter-level dielectric film 38 is formed on the exposed metallayer 36 and dielectric layer 35. A barrier layer 39 is formed on thedielectric layer 38, a metal layer 40 is formed on the barrier layer 39that contacts metal layer 36, and an inter-level dielectric film 41 isformed on the exposed metal layer 40 and dielectric layer 38. At the topof the bond pad 50, a barrier layer 42 is formed on the dielectric layer41, and a metal layer 43 is formed on the barrier layer 42 that contactsmetal layer 40. There may also be a seed layer (not shown) between themetal layers 36, 40, and 43 and passivation layers 38, and 41,respectively. The metal wire 44 is bonded to the metal layer 43 byball-bond material 45. These additional metal layers above the layer ofCrO in the bond pad could be used to construct a bond pad alsocontaining aluminum. As a result, the second method could be used forvarious wire bonding techniques, such as gold-wire bonding to aluminumused during assembly and packaging.

[0034] One or more of the above steps may be repeated any number oftimes.

[0035] While the invention has been described with specificity,additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details shown and described herein.Accordingly, various modifications may be made without departing fromthe spirit or scope of the general inventive concept as defined by theappended claims and their equivalents. For example, the number ofmetallization layers may vary.

What is claimed is:
 1. A method of manufacturing an integrated circuitcomprising: a. providing a wafer having an inter-level dielectric filmand a barrier layer; b. depositing a seed layer of copper on saidbarrier layer; c. electroplating copper to a thickness sufficient tofill any valleys in said inter-level dielectric film and cover an entiretop surface of said wafer; d. chemical mechanical polishing said topsurface to remove i) any excess portions of copper caused by saidelectroplating and ii) selected portions of said inter-level dielectricfilm; e. depositing a layer of CrO on said polished top surface to coverremaining portions of said copper; f. depositing a passivation layer onsaid layer of CrO and portions of said inter-level dielectric film; andg. etching said passivation layer to form a via that exposes a selectedportion of said layer of CrO.
 2. The method of claim 1 wherein saidinter-level dielectric film comprises at least one layer of an inorganiccompound selected from the group consisting of silicon oxide, siliconnitride, silicon oxynitride, and mixtures thereof.
 3. The method ofclaim 1 wherein said inter-level dielectric film is SiO₂.
 4. The methodof claim 1 wherein said inter-level dielectric film comprises at leastone layer of an organic compound.
 5. The method of claim 1 wherein saidbarrier layer comprises a material selected from the group consisting ofTa, TaN, TiN, Ti, W, WN, TiSiN, TaSiN, or mixtures thereof.
 6. Themethod of claim 1 wherein said layer of CrO has a thickness of about150-600Å.
 7. The method of claim 1 wherein said layer of CrO has athickness of about 300Å.
 8. The method of claim 1 wherein said layer ofCrO is formed by sputtering Cr in the presence of O₂ and said layer ofCrO is patterned using lithography after said layer of CrO is deposited.9. The method of claim 1 wherein said layer of CrO is formed byevaporating Cr in the presence of O₂ and said layer of CrO is patternedusing lithography after said layer of CrO is deposited.
 10. The methodof claim 1 wherein said layer of CrO is formed by autocatalytic platingCr in the presence of O₂.
 11. The method of claim 1 wherein said barrierlayer is backsputtered before said seed layer is formed to improveadhesion.
 12. The method of claim 1 wherein said seed layer is formed bysputtering.
 13. The method of claim 1 wherein said seed layer is formedby chemical vapor deposition.
 14. The method of claim 1 wherein saidpassivation layer is comprised of a compound selected from the groupconsisting of silicon dioxide, silicon nitride, silicon oxynitride,doped silicon dioxide, doped silicon nitride, doped silicon oxynitride,and mixtures thereof.
 15. The method of claim 1 wherein said passivationlayer is formed by a process selected from the group consisting ofchemical vapor deposition, spin-on dielectric glass, spinon dielectricpolymer, and combinations thereof.
 16. An integrated circuit made by themethod of claim
 1. 17. An integrated circuit comprising: a wafer havinga surface; a copper layer and an inter-level dielectric film formed onselected portions of said surface; a seed layer and a barrier layerformed between said copper layer and said inter-level dielectric film; alayer of CrO deposited substantially uniformly on top of said copperlayer; a passivation layer covering any exposed portions of said copperlayer and said inter-level dielectric film; and a via formed in saidpassivation layer, exposing a portion of said layer of CrO.
 18. A methodof manufacturing an integrated circuit comprising: a. providing a waferhaving bond pads comprised of a barrier layer, a seed layer formedthereon, and copper formed on said seed layer; b. forming a layer of CrOon said copper; c. forming a passivation layer on said layer of CrO; andd. etching said passivation layer to form a via that exposes a selectedportion of said layer of CrO.
 19. The method of claim 18 wherein saidbarrier layer comprises a material selected from the group consisting ofTa, TaN, TiN, Ti, W, WN, TiSiN, TaSiN, and mixtures thereof.
 20. Themethod of claim 18 wherein said layer of CrO has a thickness of about150-600Å.
 21. The method of claim 18 wherein said layer of CrO has athickness of about 300Å.
 22. The method of claim 18 wherein said layerof CrO is formed by sputtering Cr in the presence of O₂ and said layerof CrO is patterned using lithography after said layer of CrO isdeposited.
 23. The method of claim 18 wherein said layer of CrO isformed by evaporating Cr in the presence of O₂ and said layer of CrO ispatterned using lithography after said layer of CrO is formed.
 24. Themethod of claim 18 wherein said layer of CrO is formed by autocatalyticplating Cr in the presence of O₂.
 25. The method of claim 18 whereinsaid passivation layer is comprised of a compound selected from thegroup consisting of silicon dioxide, silicon nitride, siliconoxynitride, doped silicon dioxide, doped silicon nitride, doped siliconoxynitride, and mixtures thereof.
 26. The method of claim 18 whereinsaid passivation layer is formed by a process selected from the groupconsisting of chemical vapor deposition, spin-on dielectric glass,spin-on dielectric polymer, and combinations thereof.
 27. The method ofclaim 18 further comprising: c. depositing multiple metal interconnectlayers on said passivation layer and layer of CrO.
 28. An integratedcircuit made by the method of claim
 18. 29. An integrated circuitcomprising: a bond pad, having a barrier layer, a seed layer formed onsaid barrier layer, a copper layer formed on said seed layer, and alayer of CrO covering said copper layer, formed in an inter-leveldielectric film; and a passivation layer formed on any exposed portionsof said copper layer, said inter-level dielectric fil, and a portion ofsaid layer of CrO.